The present invention relates generally to the field of microprocessors, and more particularly to store to load data forwarding from a large number of uncommitted store instructions.
In high performance and especially out-of-order processors, operand store compare hazards contribute significantly to delays in instruction processing and check pointing. In microprocessors that execute load and store instructions out-of-order, three operand store compare hazards (store-hit-load, non-forwardable load-hit store, and persistent non-forwardable load-hit store) can occur due to reordering between dependent loads and stores. One way to alleviate these delays is to speculatively forward data form uncommitted stores to subsequent dependent loads. This forwarding is generally accomplished by keeping uncommitted store data in a queue-like structure, against which subsequent loads compare, and delivering the matching data to the load out of the queue.